Synchronous design: the right technique for digital ASICs

The synchronous design methodology for ASIC system design is illustrated. The advantages and disadvantages of this design approach are discussed. The synchronous design style has many advantages over the more popularly used asynchronous style. To be successful in designing high-density ASICs with more than 100 K gates, or high-speed ASICs with system speeds of several hundred MHz, this design approach must be adopted. However, there may be applications where the asynchronous approach is necessary, for example, in low-power CMOS circuits. Very little of the circuitry surrounding a typical ASIC is synchronous (e.g. microprocessor interfaces, memories). It is often necessary to include some asynchronous circuitry to interface to the outside world