Gate capacitance scaling and graphene field-effect transistors with ultra-thin top-gate dielectrics

Graphene has emerged recently as an attractive channel material for high frequency analog device applications. High carrier mobility and large gate capacitance are both desirable attributes for such devices. A main obstacle however in depositing thin dielectrics on graphene, with high dielectric constant is its chemical inertness. This obstacle can be overcome by either directly depositing the dielectric, e.g. using sputtering or e-beam evaporation, or by using a seed layer which provides nucleation sites for atomic layer deposition (ALD). The interfacial layer however reduces the gate capacitance and can also impact the quality of the ALD dielectric subsequently grown. Here we provide a systematic study of gate capacitance scaling of graphene field effect transistors with Al₂O₃ gate dielectric with two seed layers, oxidized aluminum and oxidized titanium. Our results show the oxidized Ti film on graphene provides a smooth surface, which allows us to use a Ti nucleation layer as thin as 6Å, and achieve uniform coverage required for the subsequent ALD. The k-value of the ALD Al₂O₃ grown on graphene using oxidized Ti as nucleation layer is 12.7, a value 2.5 times larger than the ALD Al₂O₃ grown using oxidized Al. We demonstrate graphene devices with ultra-thin top gate dielectrics, with EOT values as low as 3.5 nm.