High Read Stability and Low Leakage Cache Memory Cell

Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines during a read operation. A new nine transistor (9T) SRAM cell is proposed in this paper for simultaneously enhancing read stability and reducing leakage power consumption. The proposed 9T SRAM cell isolates the data from the bit lines during a read operation. The read static-noise-margin (SNM) of the proposed circuit is enhanced by 2times as compared to a standard 6T SRAM cell in a 65 nm CMOS technology. Furthermore, leakage power consumption of the new 9T SRAM cell is reduced by 22.9% as compared to the 6T SRAM cell. The read stability enhancement and leakage power reduction provided by the new circuit technique are also verified under process parameter variations.