An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM

Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage currents effectively. However, in order to preserve the state of the cell in standby mode, source voltage cannot be raised beyond a certain level. The maximum source voltage of an SRAM cell is determined by its hold stability in a particular process corner. Hence, in order to achieve the maximum leakage reduction, the source voltage of each individual cell must be raised up to its maximum safe level. However, any cell-based technique realizing this would be practically not feasible. In this paper, we propose an SRAM leakage reduction technique, referred to as adaptive sleep transistor biasing, which automatically fine-tunes the source voltage of individual memory blocks to their optimum level. Thus, maximum leakage savings can be expected while data is safely retained during standby mode. Preliminary study shows that the proposed scheme has the potential of providing substantial saving in leakage power over those by using the conventional techniques.