• DocumentCode
    2901942
  • Title

    Mixed-signal ASIC simulation via an analog modeling package

  • Author

    Ko, Uming ; Schenck, Stephen ; Van Eerden, B. ; Locke, Wayne ; Rumsey, Mike ; Sackett, John

  • Author_Institution
    Texas Instruments Inc., Dallas, TX, USA
  • fYear
    1990
  • fDate
    17-21 Sep 1990
  • Abstract
    Problems in designing mixed-signal ASICs come from different simulation accuracy requirements and, as a result, different modeling approaches for analog and digital circuits. The conventional design styles for mixed-signal ASICs use two separate simulators, such as a SPICE-like simulator for analog circuits and a logic simulation for digital circuits. This approach is engineering-intensive, time-consuming, and error-prone. To solve these problems, the analog modeling package (AMP) has been developed. The authors describe how the AMP presents a systematic solution to mixed-signal simulation on a pure digital-logic simulator. In the AMP, analog behavioral models are created by connecting parameterized building blocks in a schematic capture tool with SPICE-characterized data. Then a chip-level mixed-signal design verification is implemented on one simulator to eliminate errors. An analog-signal trace file is also created for automatic test program generation. This solution significantly enhances the competitiveness of mixed-signal design and development in cost, cycle-time, and first-pass success
  • Keywords
    application specific integrated circuits; circuit CAD; circuit analysis computing; circuit layout CAD; SPICE-characterized data; analog behavioral models; analog modeling package; analog-signal trace file; automatic test program generation; chip-level mixed-signal design verification; competitiveness; development cost reduction; development cycle time reduction; digital-logic simulator; first-pass success; mixed signal ASIC design; mixed signal ASIC simulation; mixed-signal simulation; schematic capture tool; systematic solution; Analog circuits; Application specific integrated circuits; Automatic testing; Circuit simulation; Costs; Digital circuits; Joining processes; Logic circuits; Logic design; Packaging;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
  • Conference_Location
    Rochester, NY
  • Type

    conf

  • DOI
    10.1109/ASIC.1990.186144
  • Filename
    186144