A 200 MHz 100 K ECL output buffer for CMOS ASICs

Author

Gabara, Thaddeus J. ; Thompson, David W.

Author_Institution

AT&T Bell Lab., Allentown, PA, USA

fYear

1990

fDate

17-21 Sep 1990

Abstract

The operation and design of 200-MHz 100 K ECL output buffers for CMOS ASICs are described. It is shown how the components of the buffer output driver transistor, gate voltage generator, and low skew input drivers are combined into unique clock and data output buffers. A section on unity gain op-amp design describes how a number of these buffers are used on an ASIC. Application guidelines (curves) to illustrate the tradeoff between the buffer frequency and the number of buffers on an ASIC application are presented. The advantages that this input buffer provides in the area of low ground bounce generation is presented. Waveforms from an ASIC with 24 balanced and 16 single ended ECL output buffers are presented

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; buffer circuits; digital integrated circuits; driver circuits; 100 K ECL compatibility; 100 K ECL logic levels; 100 K ECL output buffer; 200 MHz; CMOS ASICs; CMOS output buffer; application guidelines; balanced ECL output buffers; buffer frequency; buffer output driver transistor; clock buffers; design; design tradeoffs; gate voltage generator; ground bounce control; ground bounce generation; low skew input drivers; number of buffers; operation; single ended ECL output buffers; unity gain op-amp design; waveforms; AC generators; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Frequency; Noise generators; Noise reduction; Power dissipation; Power generation; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1990.186147

Filename

186147