Designing IEEE 1149.1 compatible boundary-scan logic into an ASIC using Texas Instrument´s Scope architecture

Author

Koeter, John

Author_Institution

Texas Instruments, Dallas, TX, USA

fYear

1990

fDate

17-21 Sep 1990

Abstract

A design that was described and simulated behaviorally in Verilog, and synthesized and optimized using Synopsys, is discussed., IEEE 1149.1-compatible (Scope) logic was added to the optimized design and Mentor gate-level simulations were performed. The performance and area impact on the chip of the Scope logic is examined and synthesis is used to minimize it

Keywords

application specific integrated circuits; circuit CAD; integrated logic circuits; logic CAD; ASIC; ASSET; IEEE 1149.1 compatible; Mentor gate-level simulations; Scope architecture; Synopsys; Texas Instruments; Verilog; boundary-scan logic; optimized design; performance/chip area impacts; Application specific integrated circuits; Decoding; Design optimization; Hardware design languages; Instruments; Libraries; Logic design; Standards development; Testing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1990.186154

Filename

186154

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2902065