Development of an ASIC macrocell design CAD system

Author

Dahl, Li-Ming ; Djaja, Gregory ; Mah, Lee ; Schucker, Douglas

Author_Institution

Motorola ASIC Div., Chandler, AZ, USA

fYear

1990

fDate

17-21 Sep 1990

Abstract

An important factor in bringing a new product to market for a successful ASIC business is the generation of design data related to macrocells, such as graphic symbols, logic simulation models, input-to-output path delays, and timing parameters for the ASIC CAD system so that ASIC customers can begin designing with the new ASIC product. Logic model generation, transition from logic to circuit simulation, circuit design with estimated parasitics, circuit verification of physical layout, and encapsulation of the macrocell design CAD flow are considered

Keywords

application specific integrated circuits; circuit CAD; circuit analysis computing; circuit layout CAD; digital integrated circuits; logic CAD; ASIC macrocell design; CAD system; circuit design; circuit simulation; circuit verification; estimated parasitics; graphic symbols; input-to-output path delays; logic simulation models; physical layout; timing parameters; Application specific integrated circuits; Circuit simulation; Circuit synthesis; Delay; Design automation; Graphics; Logic circuits; Logic design; Macrocell networks; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1990.186162

Filename

186162