Design methodology for a 1.0 μ cell-based library efficiently optimized for speed and area

The CHMOS IV ASIC 1.0 μ cell-based library avoids area and performance penalties by using a design methodology that specifically addresses cell efficiency. The library was successfully optimized for speed, cell density, chip density, and noise immunity. It is useful for both the ASIC and the internal design communities. The internal design community will adopt only those libraries which push performance to the limit. ASIC users can enjoy the performance advantages without sacrificing chip density. Having a single library that is useful for both internal and external purposes saves time and valuable resources