Interfacing test equipment to high density chip-on-tape

Test hardware interface requirements for testing high-pin-count ASIC TAB (tape automated bonding) products are discussed. Test solutions which have been proven in a production environment are described. Test-on-tape using the techniques illustrated has proven viable for high-speed bipolar gate arrays having 360 leads with 0.004 in lead width and 0.008 in lead pitch in the (outer lead bond) and test area. Successfully testing small pitch outer leads of TAB products requires the combination of electrical, mechanical, and thermal designs to be controlled within specific tolerances. The final testing of TAB ASICs is performed after all other value added processes have been completed. Therefore, an understanding of the factors which impact final test yield is essential