DocumentCode
2902543
Title
Using fault sampling to compute IDDQ diagnostic test sets
Author
Gong, Yiming ; Chakravarty, Sreejit
Author_Institution
Quickturn Syst. Inc., Mountain View, CA, USA
fYear
1997
fDate
27 Apr-1 May 1997
Firstpage
74
Lastpage
79
Abstract
A diagnostic test generation system for computing IDQQ diagnostic test sets for bridging faults in combinational circuits is presented. The system uses fault sampling. Experimental results presented show that fault sampling is a very effective method for computing diagnostic test sets, especially when the number of target faults is very large
Keywords
combinational circuits; fault diagnosis; logic testing; IDDQ diagnostic test set generation; bridging faults; combinational circuit; fault sampling; Circuit faults; Circuit testing; Fault detection; Sampling methods; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location
Monterey, CA
ISSN
1093-0167
Print_ISBN
0-8186-7810-0
Type
conf
DOI
10.1109/VTEST.1997.599444
Filename
599444
Link To Document