Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications . Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA). Unfortunately in all cases a relatively large average SS and a poor on-current have been observed. In conclusion with this work we have shown that although commonly fabricated TFETs feature source/channel interfaces normal to the transport direction, in a well-designed TFET the tunneling junction should have the same orientation of the component of the electric field modulated by the gate: only in this case the gate can effectively modulate the tunneling barrier, resulting in a steeper average SS and higher I_ON.