DocumentCode
2902741
Title
AMD´s MACH family breaks PLD speed and density barrier
Author
Agrawal, Om P.
Author_Institution
Advanced Micro Devices Inc., Sunnyvale, CA, USA
fYear
1990
fDate
17-21 Sep 1990
Abstract
The MACH (macro array CMOS high performance) family of programmable logic devices (PLDs) is described. Combining an innovative and optimized silicon architecture with an advanced 0.8 μm double-metal, electrically erasable CMOS technology, the MACH family offers the speed of low-end programmable array logic (PAL) devices (15 ns propagation delays), with the density of field programmable gate arrays (900 to 3600 equivalent gate densities), providing 3 to 12 times the functionality of existing PLD solutions
Keywords
CMOS integrated circuits; application specific integrated circuits; logic arrays; MACH; PLD; density; double metal technology; electrically erasable CMOS technology; functionality; macro array CMOS high performance; programmable logic devices; speed; CMOS logic circuits; CMOS technology; Computer architecture; Cost function; Field programmable gate arrays; Logic devices; Packaging; Programming profession; Propagation delay; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/ASIC.1990.186198
Filename
186198
Link To Document