Title :
Templates for synthesis from VHDL
Author :
Navabi, Zainalabedin ; Spillane, John
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
Two templates for synthesizable VHDL description styles and their corresponding hardware are presented. One style is at the dataflow level with an explicit clocking scheme. The other uses behavioral VHDL for describing functionality and dataflow for architectural specification
Keywords :
circuit CAD; clocks; parallel architectures; specification languages; architectural specification; behavioral VHDL; clocking scheme; dataflow; dataflow level; functionality; synthesizable VHDL description styles; Algorithm design and analysis; Clocks; Control system synthesis; Design automation; Hardware; Libraries; Resource management; Scheduling algorithm; Synthesizers; Wiring;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186201
