Power-Aware Test Data Compression for Embedded IP Cores

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, the authors propose in this paper to modify an existing test data compression technique so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded intellectual property (IP) cores. Compared to the initial solution that fill don´t-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS´89 and ITC´99 benchmark circuits and on a number of industrial circuits. Results show that up to 20times reduction in test data volume and 95% test power reduction can be obtained simultaneously