Phase Locked Loop Design for TDMA Applications

The Quasi stable lock state characteristic of conventional PLL´s is eliminated by the use of a signal activated acquisition network. The basic approach is to control a filter bandwidth and its center frequency with the incomming signal. This bandwidth/frequency control is such that the filter is initially at its wide bandwidth mode and is progressively made narrower as it is tuned to the center frequency of the incomming signal. When the amplitude of the tuned circuit output reaches a preset threshold the network is switched to the oscillator mode and then operates as a normal PLL. Computer simulation and breadboard results indicate that an acquisition time of 10 Bit times is required to achieve a probability of synchronization failure of less than 10^-8 for MSK signals operating at an Eb/No of 12dB. The design is suitable for both carrier and symbol acquisition and will operate at very high data rates.