The Very Simple CPU Simulator

The Very Simple CPU Simulator is an instructional aid for students studying computer architecture and CPU design, typically at the junior or senior level. It simulates a 4-instruction CPU introduced in the textbook Computer Systems Organization and Architecture. Students first enter an assembly language program, which is assembled by the simulator. After correcting any syntax errors, the user simulates the fetch, decode, and execute cycles of each instruction. The simulator uses animation to give students a more intuitive understanding of how the CPU fetches, decodes, and executes instructions. It shows the flow of data within the CPU´s register section and ALU. The control unit highlights asserted signals used by the rest of the CPU users may select either a hard-wired or microcoded control unit. The simulator is a recent addition to a suite Of platform-independent Java applets designed for computer architecture education. Previously developed simulators include the relatively simple CPU simulator and the relatively simple computer system simulator. All of the simulators in this suite and their source code are freely available under the terms of the GNU Public License.