DocumentCode
2903368
Title
TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure
Author
Kim, Youbean ; Song, Dongsup ; Kim, Kicheol ; Kim, Incheol ; Kang, Sungho
Author_Institution
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul
fYear
2006
fDate
Nov. 2006
Firstpage
17
Lastpage
24
Abstract
Power of scan operation is dominant factor. This paper proposed the structure to reduce scan power totally. The total scan power reduction architecture uses a duplicated transition monitoring window and sub-scan chains. Experimental results show 60% transition reduction, 2-4% fault coverage improvement, and 25% scan-in and 26% scan-out transition by the TOSCA
Keywords
built-in self test; logic testing; TOSCA; pseudorandom built-in self test; scan power; switching activity; test pattern generator; total scan power reduction architecture; transition monitoring window; transition reduction; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Logic; Monitoring; Power dissipation; Power generation; Test pattern generators; Low Power BIST; Low power test pattern generator; Pseudo-random BIST; Scan power; Switching activity;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2006. ATS '06. 15th Asian
Conference_Location
Fukuoka
ISSN
1081-7735
Print_ISBN
0-7695-2628-4
Type
conf
DOI
10.1109/ATS.2006.260987
Filename
4030735
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