Title :
Memory Fault Simulator for Static-Linked Faults
Author :
Benso, A. ; Bosio, A. ; Carlo, S. Di ; Natale, G. Di ; Prinetto, P.
Author_Institution :
Dipt. di Automatica e Informatica, Politecnico di Torino
Abstract :
Static linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design and validation a very complex task. This paper presents a memory fault simulator architecture targeting the full set of linked faults
Keywords :
fault simulation; integrated circuit testing; semiconductor storage; fault effect; memory fault simulator; memory test; static linked faults; Algorithm design and analysis; Computational modeling; Digital systems; Energy consumption; Memory architecture; Power engineering computing; Power generation; Semiconductor memory; System-on-a-chip; Testing;
Conference_Titel :
Test Symposium, 2006. ATS '06. 15th Asian
Conference_Location :
Fukuoka
Print_ISBN :
0-7695-2628-4
DOI :
10.1109/ATS.2006.260989
