• DocumentCode
    2903386
  • Title

    Memory Fault Simulator for Static-Linked Faults

  • Author

    Benso, A. ; Bosio, A. ; Carlo, S. Di ; Natale, G. Di ; Prinetto, P.

  • Author_Institution
    Dipt. di Automatica e Informatica, Politecnico di Torino
  • fYear
    2006
  • fDate
    20-23 Nov. 2006
  • Firstpage
    31
  • Lastpage
    36
  • Abstract
    Static linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design and validation a very complex task. This paper presents a memory fault simulator architecture targeting the full set of linked faults
  • Keywords
    fault simulation; integrated circuit testing; semiconductor storage; fault effect; memory fault simulator; memory test; static linked faults; Algorithm design and analysis; Computational modeling; Digital systems; Energy consumption; Memory architecture; Power engineering computing; Power generation; Semiconductor memory; System-on-a-chip; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2006. ATS '06. 15th Asian
  • Conference_Location
    Fukuoka
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2628-4
  • Type

    conf

  • DOI
    10.1109/ATS.2006.260989
  • Filename
    4030737
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2903386