Si-based tunnel field-effect transistors for low-power nano-electronics

For the Si-based TFET to beat the MOSFET performance and allow ultra-low voltage operation with re-use of a lot of the existing processing expertise, critical device optimization is needed whereby a combination of several performance boosters must be implemented. Heterostructures and an appropriate stress profile are necessary requirements. The largest design impact is expected from scaling the effective oxide thickness and the body thickness. Field-induced quantum confinement affects most theoretical predictions today and needs to be addressed in the design optimization. Overall, there are still significant challenges both in modeling, processing and characterization of the device. Progress in all three areas is required to uncover the full potential of the TFET.