Abstract :
Summary form only given. New and efficient solutions for silicon debug and diagnosis will have a highly visible impact on productivity. From prototype turn-on to volume production, sources of difficulty can include, circuit complexity, packaging, physical access, schedule, missing tool capability and the traditional infrastructure development for just go/no-go testing. The goal of this panel is to identify precise topics to drive academic research and industrial development. It is a unique continuation of an IEEE Test Technology Committee effort to examine Silicon Debug & Diagnosis. As an initial step, the focus of the Silicon Debug and Diagnosis Workshop 2006 will be to generate a template cross-industry & cross-academia list of topics. This will be summarized and, with ATS audience participation, built upon
