Title :
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
Author :
Lin, Xijiang ; Tsai, Kun-Han ; Wang, Chen ; Kassab, Mark ; Rajski, Janusz ; Kobayashi, Takeo ; Klingenberg, Randy ; Sato, Yasuo ; Hamada, Shuji ; Aikyo, Takashi
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR
Abstract :
In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from standard delay format (SDF) files, into the ATPG tool. The timing information is used to guide the test generator to detect faults through the longest paths in order to improve the ability to detect small delay detects. To avoid propagating faults through similar paths repeatedly, a weighted random method is proposed to improve the path coverage during test generation. During fault simulation, a new fault-dropping criterion, named dropping based on slack margin (DSM), is proposed to facilitate the trade-off between the test set quality and the test pattern count. The quality of the generated test set is measured by two metrics: delay test coverage and SDQL. The experimental results show that significant test quality improvement is achieved when applying timing-aware ATPG with DSM to industrial designs
Keywords :
automatic test pattern generation; fault simulation; integrated circuit testing; logic testing; detect faults; fault simulation; generated test set; high quality at-speed testing; small delay defects; standard delay format; test generator; timing information; timing-aware ATPG; Added delay; Automatic test pattern generation; Circuit faults; Circuit testing; Fault detection; Frequency; Logic circuits; Manufacturing; Robustness; Timing;
Conference_Titel :
Test Symposium, 2006. ATS '06. 15th Asian
Conference_Location :
Fukuoka
Print_ISBN :
0-7695-2628-4
DOI :
10.1109/ATS.2006.261012