DocumentCode :
2903864
Title :
CAST: A page-level FTL with compact address mapping and parallel data blocks
Author :
Zhiyong Xu ; Ruixuan Li ; Cheng-Zhong Xu
Author_Institution :
Shenzhen Inst. of Adv. Technol., Shenzhen, China
fYear :
2012
fDate :
1-3 Dec. 2012
Firstpage :
142
Lastpage :
151
Abstract :
NAND flash memory based Solid State Drive (SSD) is increasingly popular as one of the major non-volatile storage devices. Due to the superior performance and energy efficiency properties, it becomes an important complimentary device between the main memory and the traditional mechanical Hard Disk Drive (HDD). It is also anticipated to substitute HDD as the mainstream secondary storage. Today, flash memory is widely used in embedded systems, hand-held devices, personal computers and even enterprise computer systems. To access the data on the flash, a software component called Flash Translation Layer (FTL) has to be applied to convert the file system logical address into the corresponding physical address. FTL has great impacts on the system overall performance. Numerous FTL algorithms have been proposed in the past decade. DFTL is one of the most popular page-level address mapping FTL algorithms. It has been considered to have the best flexibility. However, it has extra mapping information I/O overhead and cannot always achieve the optimal performance. In this paper, we propose CAST, a novel and efficient pagelevel FTL algorithm to relieve this issue. CAST reserves a small portion of embedded SRAM to cache most recently accessed logical-physical address mapping information. Unlike DFTL, we use a compact packing methodology. Consecutive logical-physical page mapping information is represented with only a single entry. Thus, more address mapping information can be maintained in the caching table, and the cache hit rates can be increased. To improve the garbage collection efficiency, CAST maintains multiple current data blocks simultaneously. When a new data write request comes, the system can select an appropriate one to conduct the process based on the request issuer and/or logical address information. Our simulation results show that CAST outperforms DFTL under various workloads and it can reduce the number of erase operations and decrease the I/O response time sign- ficantly.
Keywords :
NAND circuits; SRAM chips; cache storage; disc drives; flash memories; hard discs; parallel processing; CAST; FTL; HDD; NAND flash memory; SRAM; SSD; compact address mapping; embedded systems; enterprise computer systems; flash translation layer; hand-held devices; hard disk drive; nonvolatile storage devices; page level FTL; parallel data blocks; personal computers; software component; solid state drive; Algorithm design and analysis; Ash; Data structures; Flash memory; Portable computers; Random access memory; Demand-based FTL (DFTL); Flash Translatio Layer (FTL); Multi-Level Cell (MLC); NAND flash memory; SingleLevel Cell (SLC); Solid-State Drive (SSD);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Performance Computing and Communications Conference (IPCCC), 2012 IEEE 31st International
Conference_Location :
Austin, TX
ISSN :
1097-2641
Print_ISBN :
978-1-4673-4881-2
Type :
conf
DOI :
10.1109/PCCC.2012.6407747
Filename :
6407747
Link To Document :
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