2903902

A New Method for Generating Tests for Delay Faults in Non-Scan Circuits

Agrawal, Pulin ; Agrawal, Vishwani D.

AT&T Bell Laboratories

1992

4-7 Jan 1992

4

11

Circuit faults; Circuit testing; Delay effects; Flip-flops; Logic testing; Propagation delay; Robustness; Sequential analysis; Sequential circuits; Synchronous generators;

English

ieee

VLSI Design, 1992. Proceedings., The Fifth International Conference on

1063-9667

0-8186-2465-5

conf

10.1109/ICVD.1992.658013

658013