DocumentCode :
2904066
Title :
Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction
Author :
Tsai, Po-Chang ; Wang, Sying-Jyan
Author_Institution :
Dept. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung
fYear :
2006
fDate :
20-23 Nov. 2006
Firstpage :
225
Lastpage :
230
Abstract :
This paper presents multi-mode segmented scan architecture. Three operation modes are supported: broadcast, multicast, and serial. Efficient test data compression can be achieved under this architecture with limited hardware overhead. An efficient two-way partitioning algorithm is given to construct multicast-mode configurations. Finally, we present a layout-aware scan chain routing for test compaction, which has not yet explored by the researchers. Experimental results show that most of the serial scan operations can be replaced by multicast operations, and thus achieve much better compression rate
Keywords :
automatic test equipment; boundary scan testing; data compression; design for testability; layout-aware scan chain routing; multicast operations; multicast-mode configurations; multimode segmented scan architecture; serial scan operations; test compaction; test data compression; test time reduction; two-way partitioning algorithm; Broadcasting; Circuit testing; Compaction; Computer architecture; Computer science; Hardware; Instruction sets; Registers; Routing; Test data compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2006. ATS '06. 15th Asian
Conference_Location :
Fukuoka
ISSN :
1081-7735
Print_ISBN :
0-7695-2628-4
Type :
conf
DOI :
10.1109/ATS.2006.261024
Filename :
4030772
Link To Document :
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