A Practical CMOS Companding Sinh Lossy Integrator

This paper outlines the design and simulated performance of a novel, current-mode, companding, Class-AB, Sinh lossy integrator. Prior Sinh filter designs utilize current conveyor-like blocks which incorporate both N- and P-type devices in alternate cascode arrangement to process the split-ted phases of the input. However, if these blocks were to be designed in weak inversion CMOS, the bulks of all the devices involved should be connected to their respective sources for accurate exponential/logarithmic conformity, which dictates the use of a triple-well process. Triple-well processes, apart from the fact that are not always available, have increased parasitics compared to twin-well ones, making the design and optimization of these already complicated filters a rather difficult one. In this paper, we present a new Sinh lossy integrator circuit that uses (either N- or) P-type devices rendering it to be practically realizable in any standard twin-well process. The circuit has been designed in 0.35mum AMS CMOS process with all simulation results obtained from Cadence Design Frameworkreg. The resulting lossy integrator exhibits a simulated input dynamic range greater than 120dB with only one integrating capacitor, while dissipating 0.3muW of power.