DFT of the Cell Processor and its Impact on EDA Test Softwar

Author

Bushard, Louis ; Chelstrom, Nathan ; Ferguson, Steven ; Keller, Brion

Author_Institution

IBM Corp., Rochester, MN

fYear

2006

fDate

20-23 Nov. 2006

Firstpage

369

Lastpage

374

Abstract

This paper describes aspects of the Cell processor DFT and its effects on the EDA software used to process it. The Cell processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processor had to support Logic BIST, Memory BIST, OPMSR+, SerDes I/O-WRAP as well as traditional scan-based ATPG all using a free-running high-speed clock

Keywords

automatic test software; built-in self test; design for testability; electronic engineering computing; integrated circuit testing; logic design; microprocessor chips; DFT; EDA test software; Logic BIST; Memory BIST; OPMSR+; SerDes I/O-WRAP; cell processor; complex multi-core design; design for testability; high frequency clocks; scan ATPG; Automatic test pattern generation; Built-in self-test; Clocks; Electronic design automation and methodology; Frequency; Logic; Microwave integrated circuits; Pipelines; Random access memory; Software testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2006. ATS '06. 15th Asian

Conference_Location

Fukuoka

ISSN

1081-7735

Print_ISBN

0-7695-2628-4

Type

conf

DOI

10.1109/ATS.2006.260957

Filename

4030793

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2904463