Evaluation techniques for on-line testing of robust systems based on critical tasks distribution

The process of designing robust digital systems is getting heavier and longer due to the increase of functional complexity and circuit sensitiveness [1][2]. Furthermore, aerospace and automotive electronics are including more digital systems with critical tasks distribution among several single and cheaper modules. Although collaborative hardening is providing very interesting results in terms of cost and reliability, the design process becomes more difficult. Redundant tasks, hardware and software, must be evaluated together with the global and local error mitigation techniques. Also, network links affect error propagation and mitigation. Finally, the error accumulation must be considered in these systems working in harsh conditions. In this paper we present a general method for evaluating the Single Bit Upsets (SBU) sensitivity of complex digital systems with critical tasks distribution and collaborative hardening. This method performs a detailed analysis of signal integrity along system operation thanks to hardware emulation in the early steps of the design cycle.