DocumentCode :
2904497
Title :
Design for Testability of Software-Based Self-Test for Processors
Author :
Nakazato, Masato ; Ohtake, Satoshi ; Inoue, Michiko ; Fujiwara, Hideo
Author_Institution :
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Kansai Science City
fYear :
2006
fDate :
Nov. 2006
Firstpage :
375
Lastpage :
380
Abstract :
In this paper, the authors propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency in a sense that the proposed method completely resolves the problem of error masking. Moreover, the proposed method adds only observation points to the original design, and it enables at-speed testing and does not induce delay overhead
Keywords :
automatic test pattern generation; automatic test software; built-in self test; design for testability; logic testing; microprocessor chips; design for testability; error masking problem; faults detected; processors; software self-test; test generation; test program templates; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Delay; Design for testability; Energy consumption; Fault detection; Software testing; Test pattern generators; design for testability; error masking; processor; software-based self-test; template; test program;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2006. ATS '06. 15th Asian
Conference_Location :
Fukuoka
ISSN :
1081-7735
Print_ISBN :
0-7695-2628-4
Type :
conf
DOI :
10.1109/ATS.2006.260958
Filename :
4030794
Link To Document :
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