DocumentCode
2904519
Title
High-speed Huffman decoder architectures
Author
Parhi, Keshab K.
Author_Institution
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear
1991
fDate
4-6 Nov 1991
Firstpage
64
Abstract
The author presents pipelined and parallel architectures for high-speed implementation of Huffman decoders using look-ahead computation techniques. Huffman decoders are used in high-definition television, video, and other data compression systems. The achievable speed in these decoders is inherently limited due to their sequential nature of computation. The unequal code word length of the Huffman code words makes it difficult to apply look-ahead. This problem is overcome by representing Huffman decoders as finite state machines which can exploit look-ahead. The proposed approach is useful for high-speed Huffman decoder implementations where the number of symbols of the decoder is low
Keywords
computerised signal processing; decoding; parallel architectures; pipeline processing; Huffman code; finite state machines; high-speed Huffman decoder; look-ahead computation; parallel architectures; pipeline architectures; unequal code word length; Automata; Computer architecture; Concurrent computing; Data compression; Decoding; HDTV; High definition video; Parallel architectures; TV; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 1991. 1991 Conference Record of the Twenty-Fifth Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
0-8186-2470-1
Type
conf
DOI
10.1109/ACSSC.1991.186415
Filename
186415
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