Abstract :
As the latest process technologies are combined with steadily increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. This in turn may result in costly tester reloads and unacceptable test application times. In this paper the authors present a finite memory test response compactor (a class of compactors originally proposed in Rajski et al., 2003) which is diagnosis friendly. The latter is important to maintain throughput on the test floor (Stanojevic et. al., 2005, Leininger et. al., 2002). Yet, the compactor has comparable performance to other schemes Rajski et al., 2003, Mitra et al., 2004, Mitra et al., 2004) when it comes to `X´ tolerance and aliasing
Keywords :
boundary scan testing; built-in self test; design for testability; BIST; DFT; X aliasing; X tolerance; finite memory compactor; manufacturing test; scan test data volume; scan test vectors; test floor; test response compactor; Automatic test pattern generation; Built-in self-test; Circuit faults; Circuit testing; Costs; Delay; Design for testability; Logic testing; Manufacturing; Semiconductor device testing; BIST; DFT; aliasing; compaction; diagnostics.;
