Title :
Highly efficient digital CMOS accelerator for image and graphics processing
Author :
Margala, Martin ; Lin, Rong
Author_Institution :
Electr. & Comput. Eng. Dept., Rochester Univ., NY, USA
Abstract :
This paper presents a novel high-bandwidth digital accelerator for image and graphics processing applications. The proposed architecture outperforms previously proposed processing-in-memory architectures in speed, area and power by up to several orders of magnitude. Several variations of the design have been implemented in 2.5 V 0.25 μm and 1.8 V 0.18 μm CMOS technology.
Keywords :
CMOS digital integrated circuits; computer graphics; coprocessors; image processing equipment; integrated circuit design; 0.18 micron; 0.25 micron; 1.8 V; 2.5 V; CMOS technology; area performance; design variations; digital CMOS accelerator; graphics processing; high-bandwidth digital accelerator; image processing; power performance; processing-in-memory architectures; speed performance; Application software; CMOS process; CMOS technology; Computer architecture; Computer graphics; Energy consumption; Integrated circuit technology; Portable computers; Power engineering computing; Random access memory;
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
DOI :
10.1109/ASIC.2002.1158043
