SoC gate level design migration

A successful industrial product has a lifespan of 20 or more years. Off-the-shelf ICs and ASICs both rely on fabrication processes which are obsolete far sooner. The modern ASIC design process offers excellent portability along with HDL (hardware description language) device descriptions and test benches. Older designs, typically captured as gates in schematics and validation files in proprietary simulation environments, make porting a challenge. The validity of, and issues with, converting a legacy gate-level design are presented. There is a trend in certain SoC designs to initiate gate level migrations in order to meet time-to-market pressures. We have developed a design flow for gate-level design migrations and experiences using this flow are discussed.