DocumentCode :
2905723
Title :
Hardware control of a real-time multichannel digital signal processing system
Author :
Weeks, William A. ; Chittenden, Constance T. ; Heilman, Paul M.
Author_Institution :
SRI Int., Menlo Park, CA, USA
fYear :
1991
fDate :
4-6 Nov 1991
Firstpage :
423
Abstract :
SRI International has developed a high-performance parallel signal processing system for use in real-time applications. The system consists of multiple analog input and output (I/O) channels linked by an array of digital signal processing (DSP) elements. System performance requires that multiple output samples, which depend on the input data, be generated immediately following the acquisition of the input samples. Two innovative features of the system are an ensemble of DSP boards, each of which contains eight AT&T DSP32C processors, and a network of multiplexed data paths and scheduling hardware. The latter feature solves the I/O bottleneck problem common to commercial DSP approaches and results in higher data throughput than is possible with run-time software scheduling. Planned improvements to the design are discussed
Keywords :
digital signal processing chips; parallel architectures; real-time systems; AT&T DSP32C processors; DSP boards; DSP modules; data throughput; hardware configurations; hardware control; high-performance parallel signal processing system; multiple analogue input channels; multiple output channels; multiplexed data paths; real-time multichannel digital signal processing system; scheduling hardware; Array signal processing; Control systems; Delay; Digital signal processing; Finite impulse response filter; Hardware; Processor scheduling; Real time systems; Signal processing; System performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers, 1991. 1991 Conference Record of the Twenty-Fifth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
ISSN :
1058-6393
Print_ISBN :
0-8186-2470-1
Type :
conf
DOI :
10.1109/ACSSC.1991.186485
Filename :
186485
Link To Document :
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