DocumentCode :
2905768
Title :
Impact of technology scaling and packaging on dynamic voltage scaling techniques
Author :
Duarte, D. ; Vijaykrishnan, N. ; Irwin, M.J. ; Tsai, Y.-F.
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
fYear :
2002
fDate :
25-28 Sept. 2002
Firstpage :
244
Lastpage :
248
Abstract :
This paper studies how the effectiveness of various dynamic voltage scaling mechanisms is affected by technology scaling and system activity. We show that Vdd scaling maintains its effectiveness while Vth scaling and supply gating become more efficient as the feature size decreases. We also discuss the impact of packaging and. provide tools for bringing it early into the design process. In this way, short-term and long-term savings are identified, with the latter providing additional energy savings up to 10.2%, on average.
Keywords :
integrated circuit design; integrated circuit modelling; integrated circuit packaging; leakage currents; logic design; logic simulation; low-power electronics; thermal analysis; thermal management (packaging); DVS effectiveness; DVS technology scaling/packaging impact; design process packaging tools; die temperature modeling; dynamic voltage scaling techniques; feature size decrease; leakage-oriented techniques; power reduction techniques; short-term/long-term energy savings; supply gating efficiency; system activity; Computer science; Dynamic voltage scaling; Energy consumption; Equations; Maintenance engineering; Packaging; Pipeline processing; Process design; Temperature; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
Type :
conf
DOI :
10.1109/ASIC.2002.1158064
Filename :
1158064
Link To Document :
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