Title :
Experimental evaluation of a compiler-based cache energy optimization strategy
Author :
Kandemir, M. ; Kolcu, I. ; Kadayif, I.
Author_Institution :
Pennsylvania State Univ., University Park, PA, USA
Abstract :
In this paper, we present experimental results from an optimization strategy that aims at reducing the per access energy cost for direct-mapped data caches. We have developed a compiler algorithm that uses access pattern analysis to determine those references that are certain to result in cache hits (called ´certain hits´) in a virtually-addressed, direct-mapped data cache. After detecting such references, the compiler substitutes the corresponding load operations with ´energy-efficient loads´ that access only the data array of the cache instead of both tag and data arrays. This tag access elimination, in turn, reduces the per access energy consumption for data accesses. Our experimental results indicate that certain hits constitute a large percentage of total hits. They also show that even our most conservative strategy improves the data cache energy consumption by 11% on the average.
Keywords :
cache storage; circuit CAD; circuit optimisation; circuit simulation; integrated circuit design; integrated circuit modelling; logic CAD; logic simulation; microprocessor chips; optimising compilers; access pattern analysis compiler algorithms; certain cache hit references; compiler-based cache energy optimization strategies; energy-efficient load operations; per access energy consumption; per access energy cost reduction; tag access elimination; tag/data array accesses; virtually-addressed direct-mapped data caches; Cache memory; Costs; Energy consumption; Energy efficiency; Interleaved codes; Optimizing compilers; Pattern analysis; System-on-a-chip;
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
DOI :
10.1109/ASIC.2002.1158074