State assignment selection tests for pass transistor asynchronous sequential circuits

State assignment selection procedures using minimum transistor count or maximum speed of operation as selection metrics for pass transistor asynchronous sequential circuits are presented. Asynchronous sequential circuits avoid many problems facing high speed VLSI synchronous sequential circuits and therefore are becoming a viable alternative to clocked synchronous circuits. State assignment generation is a more complex process in the asynchronous case and produces many valid assignments. The authors present easy to use procedures for selecting the best assignments using these selection metrics