Design of enhanced differential cascode voltage switch logic (EDCVSL) circuits for high fan-in gate

Author

Kang, Dae Woom ; Kim, Yong-Bin

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

fYear

2002

fDate

25-28 Sept. 2002

Firstpage

309

Lastpage

313

Abstract

In this paper, a new logic-style, enhanced differential cascode voltage switch logic (EDCVSL), is presented for high performance and low power VLSI. EDCVSL simplifies the logic tree of DCVSL, and dramatically reduces the number of interconnects by eliminating the complementary inputs, while maintaining the features of DCVSL. Simulation results of EDCVSL show less power consumption compared to the traditional DCVSL architecture, while EDCVSL keeps DCVSL´s advantages.

Keywords

CMOS logic circuits; VLSI; circuit simulation; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; logic design; logic gates; logic simulation; CMOS differential logic families; CMOS enhanced differential cascode voltage switch logic circuits; DCVSL architecture; DCVSL logic tree simplification; EDCVSL logic-style power consumption; complementary inputs; high fan-in gates; high performance/low power VLSI; interconnect reduction; CMOS logic circuits; Integrated circuit interconnections; Logic circuits; Logic design; Logic gates; MOS devices; Pulse inverters; Switches; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2002. 15th Annual IEEE International

Print_ISBN

0-7803-7494-0

Type

conf

DOI

10.1109/ASIC.2002.1158076

Filename

1158076