DocumentCode :
2906040
Title :
Partitioning considerations in systolic array design
Author :
Kuchibhotla, Prashanth ; Rao, Bhaskar D.
Author_Institution :
California Univ., San Diego, La Jolla, CA, USA
fYear :
1991
fDate :
4-6 Nov 1991
Firstpage :
530
Abstract :
Efficient scheduling techniques are developed for methods in partitioning problems that do not match the array size exactly. In particular, scheduling for the locally-parallel-globally-sequential (LPGS) technique and the locally-sequential-globally-parallel (LSGP) technique are developed. The scheduling procedure exploits the fact that after LPGS and LSGP partitioning, the locality constraints get modified, allowing the use of certain interconnections that were not available before. The scheduling method allows development of a flexible scheduling order for LPGS that is useful in evaluating a trade-off between execution time and the size of the partitioning buffers. The scheduling techniques are illustrated with the help of matrix multiplication and QR decomposition examples
Keywords :
circuit layout CAD; matrix algebra; scheduling; systolic arrays; QR decomposition; locality constraints; locally-parallel-globally-sequential; locally-sequential-globally-parallel; matrix multiplication; partitioning problems; scheduling techniques; systolic array design; Algorithm design and analysis; Broadcasting; Hardware; Matrix decomposition; Partitioning algorithms; Processor scheduling; Signal design; Signal processing algorithms; Systolic arrays; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers, 1991. 1991 Conference Record of the Twenty-Fifth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
ISSN :
1058-6393
Print_ISBN :
0-8186-2470-1
Type :
conf
DOI :
10.1109/ACSSC.1991.186505
Filename :
186505
Link To Document :
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