Using ATPG for clock rules checking in complex scan designs

Structured Design-For-Testability (DFT) employs automated Design-Rules-Checking (DRC) to ensure a design is testable and test patterns can be produced using Automated Test Pattern Generation (ATPG). Central to DRC are ATPG-related clock rules. This paper defines a robust set of clock rules and their implementation for scan designs. It then extends clock-rule-violation detection beyond test requirements, which provides fast clock verification early in the design cycle, complementing the more complex and slower timing tools. Results on a large microprocessor design show the applicability of ATPG-based timing verification