An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

We propose a cryptographic accelerator for IPsec by using the NEC electronics´ dynamically reconfigurable processor (DRP). In our system, an embedded processor and DRP are integrated in a system-on-a-chip (SoC) and multiple cryptographic tasks can be accelerated by DRP. Moreover, the virtual hardware mechanism, which dynamically changes its configuration data set, is introduced to realize more tasks on DRP. The evaluation results show that the throughput of each implemented cryptographic task outperformed a MIPS compatible embedded processor from 1.6 times to 7.8 times. In addition, it is shown that 80.7% of the run-time configuration overhead can be reduced by background configuration based on the double buffering method