DocumentCode
2906209
Title
Design of a 30 MHz, 32/16/8-points DCT processor with Phideo
Author
Lippens, P.E.R. ; Van Meerbergen, J.L. ; Verhaegh, W.F.J. ; Grant, D.M. ; van der Werf, A.
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
fYear
1994
fDate
1994
Firstpage
24
Lastpage
32
Abstract
This paper describes the VLSI implementation of a 30 MHz DCT processor which is able to perform 8-point, 16-point or 32-point DCT operations. The design is done using the Phideo design methodology and tool set. The paper shows how tools like those in the Phideo suite help the designer to evaluate design decisions. The interaction with the tools is at a high level of abstraction, and details of the implementation like clock level timing and control are filled in by the tools
Keywords
VLSI; 30 MHz; DCT processor; Phideo design methodology; Phideo tool set; VLSI implementation; Clocks; Design methodology; Discrete cosine transforms; Frequency; Laboratories; Matrix decomposition; Timing; Transform coding; Very large scale integration; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Signal Processing, VII, 1994., [Workshop on]
Conference_Location
La Jolla, CA
Print_ISBN
0-7803-2123-5
Type
conf
DOI
10.1109/VLSISP.1994.574727
Filename
574727
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