FPGA architecture for standby power management

Modern reconfigurable architectures like FPGAs have emerged as a viable platform for system implementation. However, the luxury of system implementation along with the flexibility to reprogram the device, comes at the cost of substantial hardware overhead that has made such fabrics extremely power hungry. In current nanometer designs, static or leakage power has emerged as a dominant component in total power consumption. In order to evolve under aggressive technology scaling, modern reconfigurable fabric must evolve with new architectures, design methodologies and CAD tools. In this paper we present an architecture for standby power management in programmable fabrics. We analyze various trade-offs of design variables associated with such architectures