DocumentCode
2906357
Title
FPGA implementation of a subspace tracker based on a recursive unitary ESPRIT algorithm
Author
Boonyanant, Phakphoom ; Tan-a-ram, Surapol
Author_Institution
Nat. Electron. & Comput. Technol., Thailand
Volume
A
fYear
2004
fDate
21-24 Nov. 2004
Firstpage
547
Abstract
This paper presents an FPGA implementation of a subspace tracker. The proposed design exploits a low-complexity property of a fast recursive ESPRIT algorithm. In addition, by applying a unitary transform, the system can be formulated in terms of real-valued computations. The simulation and real-time implementation are given based on 2-million gate Virtex II FPGA from Xilinx.
Keywords
adaptive signal processing; array signal processing; direction-of-arrival estimation; field programmable gate arrays; research initiatives; DOA; FPGA implementation; Virtex II FPGA; Xilinx; adaptive beamforming; direction-of-arrival estimation; recursive unitary ESPRIT algorithm; subspace tracker; uniform linear array estimation; unitary transform; Field programmable gate arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2004. 2004 IEEE Region 10 Conference
Print_ISBN
0-7803-8560-8
Type
conf
DOI
10.1109/TENCON.2004.1414478
Filename
1414478
Link To Document