Title :
Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration
Author :
Xia, Tian ; Wyatt, Stephen ; Ho, Rupert
Author_Institution :
Dept. of Electr. & Comput. Eng., Vermont Univ.
Abstract :
In this paper, a new adaptive PLL is implemented. This PLL employs a simple yet effective jitter test circuit to monitor the PLL jitter performance. Additionally, it uses a digital control unit to dynamically adjust the switched loop filter to suppress the jitter. By using this structure, the trade-off between the PLL locking speed and jitter performance can be balanced
Keywords :
digital phase locked loops; integrated circuit noise; integrated circuit testing; interference suppression; timing jitter; PLL jitter; adaptive PLL; digital control unit; jitter test circuit; phase locked loop self-calibration; switched loop filter; Automatic testing; Circuit noise; Circuit testing; Clocks; Digital control; Digital filters; Monitoring; Phase locked loops; Power supplies; Timing jitter;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on
Conference_Location :
Arlington, VA
Print_ISBN :
0-7695-2706-X
DOI :
10.1109/DFT.2006.26
