LMSGEN: a prototyping environment for programmable adaptive digital filters in VLSI

This paper describes a VHDL library-based design methodology for programmable and adaptive (LMS and block LMS) FIR digital filters-LMSGEN. Sample rates ranging from 8 to 70 Mbaud can be achieved by choosing appropriate building blocks from the library. Using LMSGEN, a highly parallel 12.5 Mbaud 60-tap block LMS/programmable FIR filter was designed and tested in 0.8 μm CMOS technology with 81.95 mm² silicon area. A 12.5 Mbaud 64-tap programmable FIR filter was also designed and tested in 0.8 μm CMOS technology with 61.35 mm² silicon area. Power dissipation can be minimized through the use of multiple parallel processing functional units at lower clock speeds, at the choice of the designer