Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates

Author

Granhaug, Kristian ; Aunet, Snorre

Author_Institution

Dept. of Informatics, Oslo Univ.

fYear

2006

fDate

4-6 Oct. 2006

Firstpage

20

Lastpage

28

Abstract

This paper presents simulations of 3 different implementations of the minority-3 function, with special focus on mismatch analysis through statistical Monte Carlo simulations. The simulations clearly favors the minority-3 mirrored gate, and a gate-level redundancy scheme, where identical circuits with the same input drive the same output-node, is further explored as a means of increasing fault- and defect-tolerance. Important tradeoffs between supply voltage, redundancy and yield are revealed, and V_DD = 175 mV is suggested as a minimum useful operating voltage, combined with a redundancy factor of 2

Keywords

CMOS logic circuits; Monte Carlo methods; fault tolerance; integrated circuit yield; logic gates; logic testing; low-power electronics; redundancy; 175 mV; defect tolerance; fault tolerance; gate-level redundancy scheme; integrated circuit yield; minority-3 mirrored gate; mismatch analysis; multifunction subthreshold CMOS gates; statistical Monte Carlo simulations; Analytical models; Circuit faults; Circuit simulation; Digital circuits; Energy consumption; Informatics; Performance analysis; Redundancy; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on

Conference_Location

Arlington, VA

ISSN

1550-5774

Print_ISBN

0-7695-2706-X

Type

conf

DOI

10.1109/DFT.2006.35

Filename

4030912