Title :
Characterizing dynamic and leakage power behavior in flip-flops
Author :
Ramanarayanan, R. ; Vijaykrishnan, N. ; Irwin, M.J.
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
This paper presents a detailed analysis of power consumption in a variety of flip-flop designs including scannable latches. The analysis was performed by implementing and simulating the different designs using 70 nm, 1 V CMOS technology. First, we perform a detailed characterization of the dynamic power consumption due to output transitions, and that due to clock and data transitions when there is no output transition. Further, we also characterize the leakage behavior of each of the flip-flop designs and specifically, characterize the input dependence of leakage.
Keywords :
CMOS logic circuits; circuit simulation; flip-flops; integrated circuit design; integrated circuit modelling; leakage currents; logic design; logic simulation; 1 V; 70 nm; CMOS flip-flops; clock transitions; data transitions; flip-flop dynamic/leakage power behavior characterization; leakage input dependence; output transitions; power consumption analysis; scannable latches; CMOS technology; Clocks; Computer science; Design engineering; Energy consumption; Flip-flops; Master-slave; Power engineering and energy; Propagation delay; Timing;
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
DOI :
10.1109/ASIC.2002.1158098
