DocumentCode
2906522
Title
Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects
Author
Yellambalase, Yadunandana ; Choi, Minsu ; Kim, Yong-Bin
Author_Institution
Dept. of Electr. & Comput. Eng., Missouri-Rolla Univ., Rolla, MA
fYear
2006
fDate
Oct. 2006
Firstpage
98
Lastpage
106
Abstract
With the recent development of nanoscale materials and assembly techniques, it is envisioned to build high-density reconfigurable systems which have never been achieved by the photolithography. Various reconfigurable architectures have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high-density systems consisting of nanometer-scale elements are likely to have many imperfections and variations; thus, defect-tolerance is considered as one of the most exigent challenges. In this paper, we evaluate three different logic mapping algorithms with defect avoidance to circumvent clustered defective crosspoints in nanowire reconfigurable crossbar architectures. The effectiveness of inherited redundancy and configurability utilization is demonstrated through extensive parametric simulations
Keywords
fault tolerance; logic design; nanoelectronics; nanowires; reconfigurable architectures; redundancy; assembly techniques; clustered defects; configurability utilization; defect tolerance; high-density reconfigurable systems; inherited redundancy; logic mapping algorithms; nanoscale materials; nanowire crossbars repairing; photolithography; Assembly systems; Circuit testing; Clustering algorithms; Computer architecture; Lithography; Logic devices; Nanoscale devices; Nanostructures; Reconfigurable logic; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on
Conference_Location
Arlington, VA
ISSN
1550-5774
Print_ISBN
0-7695-2706-X
Type
conf
DOI
10.1109/DFT.2006.37
Filename
4030920
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