A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices

In this paper, a novel defect tolerance and test method is proposed for highly defect prone reconfigurable nanoscale devices. The method is based on searching for a fault-free implementation of functions in each configurable nanoblock. The proposed method has the advantage of not relying on defect location information (defect map). It also removes the requirement of per chip placement and routing. A simulation tool is developed and several experiments are performed on MCNC benchmarks to evaluate defect tolerance and yield achievable by the proposed method. A greedy search algorithm is also developed in this simulation program that finds a fault-free configuration of each function of an application on a nanoblock of the device. The experiments are performed for different defect rates and under different values of redundancy provided for the device model. The results show that the proposed method can achieve high yields in acceptable amount of test and reconfiguration time under very high defect densities and with minimum amount of redundancy provided in the device